HOME » DURING ENGINEERING VHDL LAB


VHDL Lab

Experiment 1

To Implement all Basic Gate- AND, OR, NAND, XOR, NOR, NOT, XNOR
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Experiment 2

To implement Adders : Full Adders and Half Adders
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Experiment 3

Implementation of Boolean Expression using Universal Gates
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Experiment 4

Implementation of Adders using Multiplexer
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